With the rapid development of semiconductor technologies, the critical dimension (CD) of semiconductor devices has been continuously reduced. Accordingly, the integration level of integrated circuits (ICs) has become higher and higher; and higher requirements for device performances have been brought out.
With the continuous reduction of the size of metal oxide semiconductor field-effect transistors (MOSFETs), the channel length of the MOSFET has to be continuously reduced to adapt to the decrease of the technology node. Consequently, shrinking the channel length is able to increase the device density of the IC chip and the switching speed of the MOSFET.
However, with the continuous reduction of the channel length, the distance between the source and the drain of the device is reduced as well. Accordingly, the control ability of the gate structure on the channel region is reduced. It is more difficult for the gate voltage to pinch off the channel. Thus, the subthreshold leakage phenomenon, i.e., short-channel effect (SCE), has become one of the critical technology issues.
To meet the requirements for the device miniaturization, semiconductor technologies have gradually transformed from planar MOSFETs to the more effective three-dimensional transistors, for example, fin field-effect transistors (FinFETs). FinFETs have sufficiently good ability to control the channels.
However, it is easy for an FinFET to have a gate-induced drain leakage (GIDL) issue when the FinFET is in operation. As a result, there is a need to solve the GIDL issues, and to improve the reliability of the fin field-effect transistors. The disclosed methods and semiconductor structures are directed to solve one or more problems set forth above and other problems in the art.